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Generation of Optimal Transition Count Tests

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1 Author(s)
Hayes, J.P. ; Department of Electrical Engineering and the Department of Computer Science, University of Southern California

The problem of generating minimum-length transition count (TC) tests is examined for combinational logic circuits whose behavior can be defined by an n-row fault table. Methods are presented for generating TC tests of length n+2 and 2n-1 for fault detection and fault location, respectively. It is shown that these tests are optimal with respect to the class of n-row fault tables in the sense that there exist n-row fault tables that cannot be covered by shorter TC tests. The practical significance of these tests is discussed.

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Computers, IEEE Transactions on  (Volume:C-27 ,  Issue: 1 )