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The list of separating edges for a switching function describes the boundary between its 1-cells and its 0-cells on the n-cube. It is shown how combinational logic can be designed by partitioning this list. The technique works from the output of the gates toward their inputs and is particularly suited for design with inverting gates (NAND, NOR). Fan-in limits are handled systematically. A necessary constraint for partitioning and a steepest descent technique for the choice of partitions are introduced. Examples for design with fan-in limits of 2 and 3 and for the classical two-stage design problem are given.