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Reduction of Depth of Boolean Networks with a Fan-In Constraint

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3 Author(s)
F. P. Preparata ; Coordinated Science Laboratory and Department of Electrical Engineering, University of Illinois ; D. E. Mulller ; A. B. Barak

In this paper we presentt family of techniques for the design of combinational networks whose objective is the reduction of the number of levels, subject to a constraint on the fan-in of the logic gates. We show that a Boolean expression with n literals and involving the connectivest AND and OR can be restructured so that the resulting network of AND and OR gates has depth at most Cllog2n + δ, where a < 0.415 and Clis 1.81, 1.38, 1.18, and 1 for maximum fan-in l of 2,3,4, and 5, respectively. If we additionally require that the amount of equipment of the resulting network be bounded by a linear function of n, it is possible to bound the depth by 2 log2n with a fan-in of at most 3.

Published in:

IEEE Transactions on Computers  (Volume:C-26 ,  Issue: 5 )