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Resolution-Oriented Fault Interrelationships in Combinational Logic Networks

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2 Author(s)
V. K. Agarwal ; Department of Electrical Engineering, The Johns Hopkins University ; G. M. Masson

This correspondence considers fault resolution as a process of applying a sequence of input vectors, called tests, to a combinational logic network in order to resolve an existing fault situation from within a given master set of faults. A functional approach based upon an extension of the well-known Boolean difference concept to fault dependent situations is described. The test sets resulting from this extension, called fault dependent test sets, are fundamental to our considerations and are shown to be obtainable in a straightforward manner from standard test sets. Two fault interrelationships are defined which are particularly relevant to the resolution problem in that they algebraically describe the inherent limitations to the degree to which the existing fault situation can be resolved from within a given master set of faults using algebraic terminal experiments and fault dependent testing. Because these interrelationships are defined from a resolution-oriented point of view, they can be seen to be somewhat more intimate than other fault interrelationships which have been previously described in the literature. Some important ramifications of these interrelationships are discussed.

Published in:

IEEE Transactions on Computers  (Volume:C-26 ,  Issue: 11 )