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The Error Latency of a Fault in a Sequential Digital Circuit

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2 Author(s)
J. J. Shedletsky ; Digital Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University ; E. J. McCluskey

In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented.

Published in:

IEEE Transactions on Computers  (Volume:C-25 ,  Issue: 6 )