Cart (Loading....) | Create Account
Close category search window
 

A new SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Xiaojun Li ; Microelectron. Reliability Eng., Univ. of Maryland, College Park, MD ; Jin Qin ; Bing Huang ; Xiaohu Zhang
more authors

CMOS very large scale integration (VLSI) circuit reliability modeling and simulation have attracted an intense research interest in the last two decades, and as a result, almost all IC reliability simulation tools now try to incrementally characterize the wearout mechanisms of aged devices in iterative ways. These tools are able to accurately simulate the device's wearout process and predict its impact on the circuit performance. Nevertheless, an excessive simulation time, a tedious device testing work, and a complex parameter extraction process often limit the popularity of these tools in the product design and fabrication stages. In this paper, a new simulation program with integrated circuits emphasis (SPICE) reliability simulation method is developed, which shifts the focus of the reliability analysis from the device wearout to the circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models have been proposed for the most common silicon intrinsic wearout mechanisms, including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability. The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current stress profiles. Then, the corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, the SPICE simulation is performed again to check the circuit functionality and analyze the impact of the device wearout on the circuit operation. Device individual wearout effect is lumped into a very limited number of SPICE circuit elements within each failure equivalent circuit model, and the circuit performance degradation and functionality are determined by the magnitude of these additional circuit elements. In this new method, it is unnecessary to perform a large number of small-step iterative SPICE simulation process as other tools required t- - o obtain the accuracy. Therefore, the simulation time is obviously shortened. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE parameters, need to be accurately characterized at each interim wearout process. Thus, the device testing and parameter extraction work are also significantly simplified. These advantages will allow the circuit designers to perform a quick and efficient circuit reliability analysis and to develop practical guidelines for reliable electronic designs

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:6 ,  Issue: 2 )

Date of Publication:

June 2006

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.