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Analysis of Memory Interference in Multiprocessors

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1 Author(s)
D. P. Bhandarkar ; Texas Instruments,Incorporated

This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The results predicted by the model are compared with some simulation results and some actual measurements on C.mmp, a multiprocessor system being built at Carnegie-Mellon University.

Published in:

IEEE Transactions on Computers  (Volume:C-24 ,  Issue: 9 )