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Hazard Correction in Synchronous Sequential Circuits

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1 Author(s)
Servit, M. ; Department of Computers, Electrotechnical Faculty, Czech Polytechnical Institute

Limitations which are placed on input and clock signals of single and double-rank synchronous sequential circuits with memory composed of level-triggered flip-flops are presented and compared with the results of Unger [1] and Curtis [2].

Published in:

Computers, IEEE Transactions on  (Volume:C-24 ,  Issue: 3 )