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Any switching function has weighted representations, i.e., symmetric representations for which some of the arguments are repeated. We call a logic network based on such a representation a weighted realization. It is shown that a weighted realization may be implemented using a full-adder network (called a moment generator) whose outputs are fed to a multiplexer. A procedure is given to synthesize the full-adder network using the fewest possible modules and with strong coalescing of modules into multibit adders.