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A Probabilistic Approach of Designing More Reliable Logic Gates with Asymmetric Input Faults

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1 Author(s)
S. C. Hu ; Department of Electrical Engineering, Cleveland State University

Logic gates subject to asymmetric input faults may be made more reliable by employing redundant inputs. A mathematical expression for determining the optimum number of redundant inputs based on input reliabilities of the gate is developed. The development follows the theory of combinatorial probability.

Published in:

IEEE Transactions on Computers  (Volume:C-24 ,  Issue: 10 )