This paper considers a state assignment which permits one to obtain two different realizations of a sequential machine (sm). First, as a result of this assignment we obtain a double shift-register realization of an sm by means of p pairs of shift-registers, each pair of registers having the same number of stages ai(i = 1,...,p). Such realizations are called multiple-variable-length-shift-register-realizations (MVL-SRR's). Second, this state assignment permits us to obtain multimodule type iterative realizations made by means of p different module types, each of them being copied aitimes (i = l,...,p). We call these realizations multiple-variable-length-iterative-realizations (MVL-IR's). Thus any MVL-SRR or MVL-IR is uniquely specified by γp, = (a1,...,ap,).