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A Multiple-Stream Registerless Shared-Resource Processor

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1 Author(s)
Miller, E.F., Jr. ; General Research Corporation

A novel high-performance processor architecture for processing a large number of independent instruction streams is proposed and its operating behavior studied. The proposed processor operates on instruction words in a two-address format (thereby eliminating the "operating registers"), and is organized in a fashion which permits as high degree of internal buffering and pipelining. The processor has the following properties: 1) The hardware cost grows only slightly more than linearly with the overall implementation cost; 2) The overall performance is primarily dependent on the processor wordtime and is only secondarily dependent on the supporting memory cycle time; 3) All instruction stream interfaces with memory occur at special queuing (buffer) units which are used to "unscramble" the instruction streams and continually provide work for subsequent processing elements.

Published in:

Computers, IEEE Transactions on  (Volume:C-23 ,  Issue: 3 )

Date of Publication:

March 1974

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