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On-Set Realization of Fail-Safe Sequential Machines

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3 Author(s)
Diaz, M. ; Laboratoire d''Automatique et d''Analyse des Systèmes ; Geffroy, J.C. ; Courvoisier, M.

Fail-safe sequential machines can be constructed in such a way that if a failure happens in the sequential part, the ulterior functioning must carry on outside the code chosen to represent the set of states. This paper presents a study of the failures in the input combinational circuit and of the feasibility conditions of sequential machines with states coded by a k-out-of-n code. The electronic circuit is realized in a classical way (on-set realization) and must obey two hypotheses, 1) no failure on clock line C, and 2) single fault (stuck at 0 or stuck at 1) on other connections than C.

Published in:

Computers, IEEE Transactions on  (Volume:C-23 ,  Issue: 2 )