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Complete Test Sets for Logic Functions

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1 Author(s)
Reddy, S.M. ; Department of Electrical Engineering, University Iowa

The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.

Published in:

Computers, IEEE Transactions on  (Volume:C-22 ,  Issue: 11 )

Date of Publication:

Nov. 1973

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