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Self-Checking Combinational Logic Binary Counters

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1 Author(s)
Dorr, R.C. ; Bell Telephone Laboratories, Inc.

A high-speed, self-checking count circuit realization is attainable by using combinational logic and parity prediction. The utilization of combinational logic as opposed to sequential logic design generally minimizes the amount of software necessary for routine and diagnostic testing. Count circuits with parity prediction find application in stand-alone, self-checking processors.

Published in:

Computers, IEEE Transactions on  (Volume:C-21 ,  Issue: 12 )