Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Generation of Fault Tests for Linear Logic Networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Breuer, M.A. ; Department of Electrical Engineering, University of Southern California

In this note we study the problem of fault detection in linear logic networks. We introduce the concept of error vectors that indicate how the effect of a fault propagates through a network. These vectors allow one to identify redundancies in the network as well as calculate the output of the network given a fault and an input. Problems related to fault diagnosis and the detection of multiple faults are also considered.

Published in:

Computers, IEEE Transactions on  (Volume:C-21 ,  Issue: 1 )