By Topic

Codes for Error Correction in High-Speed Memory Systems—Part I: Correction of Cell Defects in Integrated Memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

This paper introduces two schemes to correct bit errors caused by defective memory cells in high-speed random-access memory systems. The schemes are addressed to word-organized memories produced by the integrated technologies. One of the two schemes calls for encoding of input information and the other does not. The schemes are simple, economical for the technologies concerned, and exhibit a regularity which makes it possible to fabricate the necessary additional hardware within the same technology.

Published in:

IEEE Transactions on Computers  (Volume:C-20 ,  Issue: 8 )