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One of the most perplexing problems confronting device designers utilizing MOS technology is the development of an effective layout design methodology. This paper describes a versatile layout design scheme for customized digital-type MOS arrays utilizing four-phase clocking schemes (ratioless logic). The analytical characterization of this layout design scheme is defined through the introduction of p-order and m-order indices. The p-order indices are assigned to members of the Boolean equation set that define the relative placement of their mechanization areas (p-diffusion structures) on the MOS array. The m-order indices are assigned to members of the term set that define their relative placements within parallel metalization channels on the MOS array. The underlying variables influencing the algorithmic derivation of quasi-optimal p-order and m-order assignments are also discussed.