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Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races

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2 Author(s)

A circuit for generating a clock pulse for asynchronous circuits is given, and when used with transition sensitive flip-flops eliminates critical races for an arbitrary state assignment. Thus the minimum number of internal variables may be used. Furthermore, logic and sequential hazards will not affect the circuit performance.

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Computers, IEEE Transactions on  (Volume:C-20 ,  Issue: 2 )