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Fast Multipliers

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2 Author(s)

A number of schemes for implementing a fast multiplier are presented and compared on the basis of speed, complexity, and cost. A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described. This multiplier multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns. The cost of the integrated circuits was less than $ 500.

Published in:

Computers, IEEE Transactions on  (Volume:C-19 ,  Issue: 2 )