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An approximate method for rapid multiplication or division with relatively simple digital circuitry is described. The algorithm consists of computing approximate binary logarithms, adding or subtracting the logarithms, and computing the approximate anti- logarithm of the resultant. Using a criteria of minimum mean square error, coefficients for the approximations are developed. An error analysis is given for three cases in which the algorithm is useful. Finally, applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.