Referenced Items are not available for this document.
A high-speed carry circuit for binary parallel adders is described. The circuit consists of emitter followers connected in series to form a transmission path for carry signals obtained from the individual bits of the adder.
Published in:
Computers, IEEE Transactions on
(Volume:C-18
,
Issue:
8
)
Date of Publication: Aug. 1969
- Page(s):
- 728 - 732
- ISSN :
- 0018-9340
- Digital Object Identifier :
- 10.1109/T-C.1969.222755
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 14 August 2006
- Issue Date :
- Aug. 1969
- Sponsored by :
- IEEE Computer Society
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