By Topic

Diagnosis of Single-Gate Failures in Combinational circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

Two procedures are presented for detecting and diagnosing arbitrary single-gate failures in combinational logic circuits. A gate is defined as any multiple-input single-output combinational circuit, and a failure is any detectable transformation of the correct gate function. The testing procedures do not require the construction of a fault table and will locate, to within an equivalence class, the faulty gate and describe its failure.

Published in:

IEEE Transactions on Computers  (Volume:C-18 ,  Issue: 3 )