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A Simplified Analysis of Processor "Look-Ahead" and Simultaneous Operation of a Multi-Module Main Memory

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2 Author(s)

This paper focuses attention upon the design of a processor and memory system which is structured to achieve a satisfactory balance of processor speed and memory speed when both the processor and input–output controller are simultaneously competing for memory service. A mathematical model is developed to investigate the degree to which the processor is capable of overlapping memory references with instruction execution as a function of respective cycle times, the number of instruction "look-aheads," the number of independent memory modules, and input–output traffic. Utilizing this model, design trade-offs and performance indices are graphically examined for a hypothetical system.

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Computers, IEEE Transactions on  (Volume:C-18 ,  Issue: 1 )