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A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction

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8 Author(s)
S. Das ; Department of EECS, University of Michigan, Ann Arbor, MI ; D. Roberts ; Seokwoo Lee ; S. Pant
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In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18mum technology. The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1% targeted error rate at a fixed frequency of 120MHz

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2006 IEEE International Conference on IC Design and Technology

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