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Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis

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3 Author(s)
Sun-Mi Park ; Dept. of Math., Korea Univ., Seoul ; Ku-Young Chang ; Do won Hong

In this paper, we present a bit-parallel multiplier for GF(2m ) defined by an irreducible pentanomial xm+xk 3 +xk 2+xk 1+1, where 1lesk 1 lesk2 lesk3 lesm/2. In order to design an efficient, bit-parallel multiplier, we introduce a shifted polynomial basis and modify a reduction matrix presented by Reyhani-Masoleh and Hasan. As a result, the time complexity of the proposed multiplier is TA+(3+[log2(m-1)])TX , where TA and TX are the delay of one AND and one XOR gate, respectively. This result matches or outperforms the previously known results. On the other hand, the proposed multiplier has the same space complexity as the previously known multipliers except for special types of irreducible pentanomials. Note that its hardware architecture is similar to that presented by Reyhani-Masoleh and Hasan

Published in:

Computers, IEEE Transactions on  (Volume:55 ,  Issue: 9 )

Date of Publication:

Sept. 2006

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