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Thermal-stress analysis of SOIC packages and interconnections

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2 Author(s)
J. H. Lau ; Hewlett-Packard Lab., Palo Alto, CA, USA ; C. G. Harkins

Thermal stresses in surface-mounted small-outline integrated-circuit (SOIC) assemblies have been studied by the finite-element method. Emphasis is placed on the effects of solder-joint geometry on package and interconnection reliability. In addition, the problem of voids in solder joints is addressed. Seven different solder-joint geometries and six different sizes of voids are considered. It was found that the effect of voids in the solder joint is to increase the stresses acting on it. Furthermore, it is concluded that the results presented herein can provide guidelines for solder-joint inspection.<>

Published in:

IEEE Transactions on Components, Hybrids, and Manufacturing Technology  (Volume:11 ,  Issue: 4 )