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High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design

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12 Author(s)
Pan, R. ; Texas Instruments Inc., Dallas, TX ; Todd, B. ; Pinghai Hao ; Higgins, R.
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This paper describes the integration of the 20V complementary drain-extended MOS (DECMOS) and fully isolated drain-extended NMOS (DENMOS) transistors into a high-volume 0.13mum CMOS technology with two additional masks. The 20V devices were optimized for Rsp-BVdss performance without compromising the advanced 1.5V CMOS performance in the 0.35mum pitch copper, low-K dielectric process flow. This cost-effective process is very competitive for the power management (PM) chip design of portable devices

Published in:

Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on

Date of Conference:

4-8 June 2006

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