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Processor architecture and data buffering

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2 Author(s)
Mulder, H. ; Dept. of Electr. Eng., Delft Univ., Netherlands ; Flynn, M.

The tradeoff between visualizing or hiding the highest levels of the memory hierarchy, which impacts both performance and scalability, is examined by comparing a set of architectures from three major architecture families: stack, register, and memory-to-memory. The stack architecture is used as reference. It is shown that scalable architectures require at least 32 words of local memory and therefore are not applicable for low-density technologies. It is also shown that software support can bridge the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local storage allocated interprocedurally outperforms scalable architectures with equal sized local memories and even some with larger sized local memories. When a small cache is added to an unscalable architecture, their performance advantage becomes significant

Published in:

Computers, IEEE Transactions on  (Volume:41 ,  Issue: 10 )