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Bit-parallel arithmetic in a massively-parallel associative processor

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3 Author(s)
Scherson, I.D. ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; Kramer, D.A. ; Alleyne, B.D.

A simple but powerful architecture based on the classical associative processor model is proposed. By distributing logic among slices of storage cells such that a number of bit-planes share a simple logic unit, bit-parallel arithmetic for massively parallel processing becomes feasible. For m-bit operands, this architecture enables complex operations such as multiplication and division to execute in O(m) cycles as opposed to O(m2 ) for bit-serial machines. Algorithms which utilize this bit-parallel property to efficiently perform operations on floating point data have been developed. The simplicity of the architecture enables its implementation using VLSI technology, and hence allows the construction of a word-parallel, bit-parallel, massively parallel (P3) computing system. Implementations of the fast Fourier transform and matrix multiplication are presented to illustrate the operation of this system

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Computers, IEEE Transactions on  (Volume:41 ,  Issue: 10 )