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Performance limits of electrical interconnections to a high-speed chip

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1 Author(s)
A. J. Rainal ; AT&T Bell Lab., Whippany, NJ, USA

An electrical model to characterize the transmission path from a printed wiring board to a high-speed chip is proposed. The model accounts for the important constraint of inductive noise. The parameter values of the transmission path depend on the physical design of the electrical interconnections. For various input signal rise times (i.e., 0.1 ns), the following results are presented: the reflected waveform, the energy of the reflected waveform, and the waveform received at the chip. These results lead to definite performance limits (e.g., bit rate) for the electrical interconnections from a printed wiring board to a high-speed chip. For advanced physical designs, tolerable pulse-waveform degradation occurs for bit rates of a few Gb/s. However, for much higher bit rates, serious pulse degradation can occur. The model can also be used to analyze high-speed connectors and general chip packages

Published in:

IEEE Transactions on Components, Hybrids, and Manufacturing Technology  (Volume:11 ,  Issue: 3 )