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A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

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7 Author(s)
Loke, A.L.S. ; Enterprise ASIC Lab. of Avago Technol., Fort Collins, CO ; Barnes, R.K. ; Wee, T.T. ; Oshima, M.M.
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This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 8 )

Date of Publication:

Aug. 2006

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