Referenced Items are not available for this document.
A CMOS analog baseband transceiver with a 13-bit, 180 MSPS pipelined ADC and dual 12-bit, 180 MSPS current-steering DACs is presented. The ADC is implemented without a dedicated track-and-hold stage, utilizes a front-end 2.5-bit stage with matched MDAC/comparator tracking circuits, and demonstrates an ENOB of 10.6 bits at 15 MHz and 9.7 bits at 100 MHz, employing a low-jitter delay-lock loop for its phasing. The dual I/Q DACs show over 62 dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
8
)
Date of Publication: Aug. 2006
- Page(s):
- 1856 - 1866
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9010786
- Digital Object Identifier :
- 10.1109/JSSC.2006.875287
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 24 July 2006
- Issue Date :
- Aug. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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