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A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

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8 Author(s)
Palaskas, Y. ; Intel Corp., Commun. Circuits Lab., Hillsboro, OR ; Taylor, S.S. ; Pellerano, S. ; Rippke, I.
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This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 8 )

Date of Publication:

Aug. 2006

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