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A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor

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21 Author(s)
Khan, A. ; Cadence Design Syst. Inc., San Jose, CA ; Watson, P. ; Kuo, G. ; Le, D.
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An electrical and physical design power optimization methodology and design techniques developed to create an IC with an ARM 1136JF-S microprocessor in 90-nm standard CMOS are presented. Design technology and methodology enhancements to enable multiple supply voltage operation, leakage current and clock rate optimization, single-pass RTL synthesis, VDD selection, power optimization and timing and electrical closure in a multi-VDD domain design are described. A 40% reduction in dynamic and a 46% reduction in leakage power dissipation has been achieved while maintaining a 355-MHz operating clock rate under typical conditions. Functional and electrical design requirements were achieved with the first silicon

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 8 )

Date of Publication:

Aug. 2006

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