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An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder

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5 Author(s)
Miles, L.H. ; Center for Microelectron. & Biomolecular Res., Univ. of Idaho, Idaho Falls, ID ; Gambles, J.W. ; Maki, G.K. ; Ryan, W.E.
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Low-density parity-check codes achieve coding performance which approaches the Shannon limit. An (8158,7136) encoder was implemented in a five-metal, 0.25-mum CMOS process. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1492 flip-flops along with a programmable 21-bit look-ahead scheme are used to achieve an 860-Mb/s data throughput for this rate 7/8 LDPC code. A comparable two-stage encoder requires 8176 flip-flops

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 8 )