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Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes

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4 Author(s)
Bhatt, T. ; Nokia Res. Center, Irving, TX ; Sundaramurthy, V. ; Stolpman, V. ; McCain, D.

We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps

Published in:

Acoustics, Speech and Signal Processing, 2006. ICASSP 2006 Proceedings. 2006 IEEE International Conference on  (Volume:4 )

Date of Conference:

14-19 May 2006

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