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An efficient locally pipelined FFT processor

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5 Author(s)
Liang Yang ; Lishan Microelectron. Corp., Xi''an, China ; Kewei Zhang ; Hongxia Liu ; Jin Huang
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The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback architecture is proposed. For length-N discrete Fourier transform computation, the dominant hardware requirements are minimal for complex multipliers log4N-1 and adders 2log4N. As an integral need of the LPPL FFT processor design, address generating and coefficient store-load structures are also presented.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 7 )

Date of Publication:

July 2006

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