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A sampled-data CMOS analog adaptive filter

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2 Author(s)
Gomez, G. ; Wright State Univ., Dayton, OH, USA ; Siferd, R.

A fully analog sampled-data CMOS adaptive filter realizing the LMS (least mean squared) adaptation on a four-tap FIR (finite impulse response) filter has been fabricated. The system uses clocked CMOS sampled-data storage, four-quadrant CMOS analog multipliers, and CMOS op amp-based arithmetic modules. For achieving higher output sampling rates and for allowing modularity, a parallel architecture has been used, implementing each filter tap separately instead of using a single time-multiplexed processing unit. The prototype chip was fabricated using double-metal double-poly 2-μm CMOS P-well technology, occupying an area of 4.0 mm2 and using ±5-V power supplies

Published in:

Aerospace and Electronics Conference, 1991. NAECON 1991., Proceedings of the IEEE 1991 National

Date of Conference:

20-24 May 1991

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