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Design of a multi-mode pipelined multiplier for floating-point applications

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2 Author(s)
A. B. Enriquez ; Air Force Inst. of Technol., Wright-Patterson AFB, Dayton, OH, USA ; K. R. Jones

The design of a VLSI multimode pipelined multiplier is presented. The multiplier is designed to accept three types of operands: IEEE FP (floating point) double- and single-format and 32-b two's complement integers. The multiplier complies fully with the IEEE standard for floating point arithmetic, with the exception of denormalized numbers. All rounding modes and exception handling are supported. The high performance of the multiplier is made possible by the use of octal Booth encoding of the multiplier to reduce the number of partial products. In addition, a novel fast carry adder, the optimized-carry-multiplexed adder, is used to accelerate the critical carry propagation paths. The multiplier is designed to operate at 40 MHz and is pipelined to allow a new operation to begin every clock cycle. Thus, 40-MFLOPS operation is possible in double-precision and integer modes. In single-precision mode, two operations are performed in parallel, yielding 80-MFLOPS performance

Published in:

Aerospace and Electronics Conference, 1991. NAECON 1991., Proceedings of the IEEE 1991 National

Date of Conference:

20-24 May 1991