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Design and architecture for a multi-mode pipelined, floating-point adder

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2 Author(s)
Gillam, K.R. ; Space Syst. Div., Los Angeles AFB, CA, USA ; Jones, K.R.

The authors present the design and architecture of a VLSI floating-point adder (FPA). The multi-mode FPA is capable of both single-precision (32-b) and double-precision (64-b) arithmetic and was developed using CMOS technology. The adder is designed for a 40-MHz clock using a pipelined architecture with a two-cycle latency. Area is minimized as hardware is shared for both single-precision and double-precision operations. Two single-precision operations in parallel are possible providing 80-MFLOPS operation. Double-precision operations yield 40-MFLOPS. With the exception of denormalized number representation, the FPA is fully compliant with the IEEE Standard, for floating-point arithmetic. In addition to floating-point operations, the FPA is capable of performing 32-b integer operations. Five format conversions can be performed by the FPA on the four formats that are supported: single-precision, double-precision, integer and block floating-point

Published in:

Aerospace and Electronics Conference, 1991. NAECON 1991., Proceedings of the IEEE 1991 National

Date of Conference:

20-24 May 1991

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