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GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links

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4 Author(s)
Campobello, G. ; Dipt. di Fisica della Materia e Tecnologie Fisiche Avanzate, Messina Univ. ; Castano, M. ; Ciofi, C. ; Mangano, D.

In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. For instance, the results of our evaluation show that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire. As a general rule, when the number of bits to be transmitted increases, the wire overhead decreases and the gate overhead remains almost the same

Published in:

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings  (Volume:2 )

Date of Conference:

6-10 March 2006