Cart (Loading....) | Create Account
Close category search window
 

A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Daglio, P. ; STMicroelectronics, Milan

Today almost all the people in the industry are talking widely about full chip mixed-signal simulation, both in pre-layout and post-layout conditions, basically for two main reasons: a large range of applications is moving from fully digital to mixed-signal and full chip simulation with parasitic components, together with IR drop analysis, is becoming strictly mandatory before going to silicon. In fact, the cost of a mask set for a 90nm or a 65nm technology is growing in an exponential way, passing the million dollar for any single mask set. For these reasons, it is strategic to set up a very complete mixed-signal design flow allowing designers to go to the silicon in a safe way with the minimum risk of failure. Nowadays, various approaches to the same problem are pursued by different organizations, sometimes privileging the fully digital modeling of the mixed-signal system and some other times setting the digital part in VHDL and keeping the analog part at transistor level, simulating the whole chip with a mixed-signal simulator. Which is the right approach? Which are the status and the reliability of the tools on the market ? Which is the acceptable trade-off among simulation speed, code coverage and precision of simulation results? This paper tries to answer to these questions proposing a fully qualified and complete mixed-signal flow for SoC verification, implemented to design applications also containing embedded flash memories

Published in:

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings  (Volume:2 )

Date of Conference:

6-10 March 2006

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.