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Formal Verification of SystemC Designs Using a Petri-Net Based Representation

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3 Author(s)
Karlsson, D. ; Dept. of Comput. & Inf. Sci., Linkopings Universitet ; Eles, P. ; Zebo Peng

This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed formal verification SystemC designs Petri-net model model checking timed temporal logic . The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments

Published in:

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings  (Volume:1 )

Date of Conference:

6-10 March 2006