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Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation

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2 Author(s)
Balarin, F. ; Cadence Berkeley Labs., CA ; Passerone, R.

Transaction level models promise to be the basis of the verification environment for the whole design process. Realizing this promise requires connecting transaction level and RTL blocks through an object called a transactor, which translates back and forth between RTL signal-based communication, and transaction level function-call based communication. Each transactor is associated with a pair of interfaces, one at RTL and one at transaction level. Typically, however, a pair of interfaces is associated to more than one transactor, each assuming a different role in the verification process. In this paper we propose a methodology in which both the interfaces and their relation are captured by a single formal specification. By using the specification, we show how the code for all the transactors associated with a pair of interfaces can be automatically generated

Published in:

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings  (Volume:1 )

Date of Conference:

6-10 March 2006

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