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An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support

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5 Author(s)
Scharwaechter, H. ; Integrated Signal Process. Syst., RWTH Aachen Univ. ; Hohenauer, M. ; Leupers, R. ; Ascheid, G.
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Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level code compilation always introduces overhead, regarding code size and performance compared to handwritten assembly code. This overhead result partially from high-level function calls that usually introduce memory accesses in order to save and reload registers contents. A key feature of many NPU architectures is hardware multithreading support, in the form of separate register files, for fast context switching between different application tasks. In this paper, a new NPU code optimization technique to use such HW contexts is presented that minimizes the overhead for saving and reloading register contents for function calls via the runtime stack. The feasibility and the performance gain of this technique are demonstrated for the Infineon Technologies PP32 NPU architecture and typical network application kernels

Published in:

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings  (Volume:1 )

Date of Conference:

6-10 March 2006