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Ultralow Power Computing with Sub-threshold Leakage: A Comparative Study of Bulk and SOI Technologies

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4 Author(s)
Raychowdhury, A. ; Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN ; Paul, B.C. ; Bhunia, S. ; Roy, K.

This paper presents a novel design methodology for ultralow power design (in bulk and double-gate SOI technology) using sub-threshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of MHz). It has been shown that a complete co-design at all levels of hierarchy (device, circuit and architecture) is necessary to reduce the overall power consumption. Simulation results of co-design on a five-tap FIR filter shows ~2.5times (for bulk) and ~3.8times (for SOI) improvement in throughput at iso-power compared to a conventional design. It has been further demonstrated that the double-gate SOI technology is better suited for sub-threshold operation

Published in:

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings  (Volume:1 )

Date of Conference:

6-10 March 2006