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A dynamically reconfigurable packet-switched network-on-chip

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3 Author(s)
T. Pionteck ; Inst. of Comput. Eng., Lubeck Univ., Germany ; C. Albrecht ; R. Koch

This paper presents the design of an adaptable NoC for FPGA based dynamically reconfigurable SoCs. At runtime, switches can be added or removed from the network, allowing to adapt the NoC to the number, size and location of currently configured hardware modules. By using dynamic routing tables, reconfiguration can be done without stopping or stalling the NoC. The proposed architecture avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs

Published in:

Proceedings of the Design Automation & Test in Europe Conference  (Volume:1 )

Date of Conference:

6-10 March 2006