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Scalable parallel implementation of exact inference in Bayesian networks

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2 Author(s)
V. K. Namasivayam ; Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA, USA ; V. K. Prasanna

We present a scalable parallel implementation for exact inference in Bayesian networks. We explore two levels of parallelization: top level parallelization which uses pointer jumping to stride across nodes; and node level parallelization which parallelizes the node level computations which are independent from each other. For a junction tree with n cliques, using p processors, the worst-case running time is (n/p(log n)) * rw where w is the clique width and r is the maximum range or number of states of the variable. We have implemented the algorithm using MPI and OpenMP. We consider three different types of input junction trees: linear junction trees, balanced trees and random junction trees, and obtained speedups of 203, 181 and 190 respectively over 256 processors

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12th International Conference on Parallel and Distributed Systems - (ICPADS'06)  (Volume:1 )

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