By Topic

Scalable hybrid designs for linear algebra on reconfigurable computing systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ling Zhuo ; Dept. of Electr. Eng., Southern California Univ., CA ; Prasanna, V.K.

Recently, reconfigurable computing systems have been built which employ field-programmable gate arrays (FPGAs) as hardware accelerators for general-purpose processors. These systems provide new opportunities for high-performance computing. In this paper, we investigate hybrid designs that effectively utilize both the FPGAs and processors in the reconfigurable computing systems. Based on a high-level computational model, we propose designs for floating-point matrix multiplication and block LU decomposition. In our designs, the workload of an application is partitioned between the FPGAs and processors in a balanced way; the FPGAs and processors work cooperatively without data hazards or memory access conflicts. Experimental results on Cray XDI show that with one Xilinx XC2VP50 FPGA (a relatively small device available in XDI) and an AMD 2.2 GHz processor, our designs achieve up to 1.4X/2X speedup over the design that employs AMD processors/FPGAs only. The performance of our designs scales with the number of nodes. Moreover, our designs achieve higher performance when improved floating-point units or larger devices are used

Published in:

Parallel and Distributed Systems, 2006. ICPADS 2006. 12th International Conference on  (Volume:1 )

Date of Conference:

0-0 0